Cornell RISC-V Interpreter
By Edward Willis (http://encw.xyz or gopher://encw.xyz)
Published May/27/2023

Today I discovered that Cornell University has a RISC-V interpreter!

https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/interpreter/#

I've been wanting to fiddle with RISC-V, but finding an SBC has been difficult.

I wrote a couple of Fibonacci sequence programs to test things out, and to
offer as example code.

Fibonacci 1
----------------
addi t0, x0, 0
addi t1, x0, 1
step:
add t2, t0, t1
add t0, x0, t1
add t1, x0, t2
jal x0, step
----------------

Fibonacci 2
----------------
addi t5, x0, 44
addi t0, x0, 0
sw t0, 0(x0)
addi t1, x0, 1
sw t1, 4(x0)
addi t4, x0, 8

step:
# new num
add t2, t0, t1
blt t2, x0, end
# setup for next
add t0, x0, t1
add t1, x0, t2
sw t2, 0(t4)
addi t4, t4, 4
bge t4, t5, res_mem
jal x0, step

#reset mem pointer
res_mem:
add t4, x0, x0
jal x0, step

end:
----------------

If this second program looks weird, it's because the interpreter displays 11
memory addresses at a time, so I wrote this to cycle through them repeatedly
until the register overflows.

That's all really. Thought I'd share the joy.

Cheers